Navigation

Algoritmer og datastrukturer

A Pipelined Multi-Core Machine with Operating System Support

Hardware Implementation and Correctness Proof

Udgivet af Springer Nature Switzerland AG

Bogdetaljer

  • Hæftet
  • 628 sider
  • Engelsk
ISBN 9783030432423
Om denne bog

This work is building on results from the book named "A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness" by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014.It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processo…

Se alle bogdetaljer →
Prissammenligning

Ingen boghandelspriser listet endnu

Denne titel er i vores bogkatalog. Butikstilbud vises her, når de er tilgængelige.

Betroet sælger:

Ingen boghandelstilbud lige nu.

Søg efter ISBN
Opdateret i dag

Boghandelspriser

Boghandel Titel Format ISBN Pris Lagerstatus Levering

Ingen boghandelstilbud endnu

Vi har titlen i kataloget. Priser vises her, når boghandlere lister den.

0.0
0 anmeldelser
5
0
4
0
3
0
2
0
1
0
0%
Anbefaler
0
Verificeret
Alle anmeldelser (0)

Ingen anmeldelser endnu

Skriv en anmeldelse

Valgfri - Kun brugt til verifikation
0 / 5000 tegn
Bogdetaljer
Forlag Springer Nature Switzerland AG
Kategori Algoritmer og datastrukturer
ISBN-13 9783030432423
EAN 9783030432423
Format Hæftet
Sprog Engelsk
sider 628
Undertitel - Hardware Implementation and Correctness Proof
Produktbeskrivelse
This work is building on results from the book named "A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness" by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014.It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features:• MIPS instruction set architecture (ISA) for application and for system programming• cache coherent memory system• store buffers in front of the data caches• interrupts and exceptions• memory management units (MMUs)• pipelined processors: the classical five-stage pipeline is extended by two pipelinestages for address translation• local interrupt controller (ICs) supporting inter-processor interrupts (IPIs)• I/O-interrupt controller and a disk

Prishistorik

Indlæser prishistorik...

Få prisalarm

Bliv underrettet, når prisen falder til dit ønskede beløb.